1. Technical Field
The present invention relates to a printed circuit board and a method of manufacturing the same.
2. Description of the Related Art
Recently, in order to cope with an increase both in signal transmission speed and density of semiconductor chips, the demand for techniques for directly mounting a semiconductor chip on a PCB is increasing. Thus, the development of a PCB having high density and high reliability capable of coping with the increasing density of the semiconductor chip is required.
The requirements for the PCB having high density and high reliability are closely related to the specs of the semiconductor chip, and may include for example circuit fineness, high electrical properties, high signal transmission structure, high reliability, high functionality and so on. Hence, there is a need for techniques which fabricate a PCB having a fine circuit pattern and micro via-holes in accordance with such requirements.
Typically, examples of a method of forming the circuit pattern of the PCB may include a subtractive process, a full additive process, and a semi-additive process. Among them, a semi-additive process enabling the circuit pattern to be very fine is currently receiving attention.
FIGS. 1 to 3 are cross-sectional views sequentially showing a method of forming a circuit pattern through a conventional semi-additive process. With reference to these drawings, the conventional method of forming a circuit pattern is described below.
As shown in FIG. 1, a via-hole 13a is formed in an insulating layer 12 which includes a metal layer 11 provided on one side thereof.
As shown in FIG. 2, an electroless plating layer 14 is formed not only on the to insulating layer 12 but also on an inner surface of the via-hole 13a. In this regard, the electroless plating layer 14 serves as a pretreatment layer adapted for an electrolytic plating process which is executed later. In other words, in order to form an electrolytic plating layer 15, the electroless plating layer 14 must achieve a critical thickness or exceed it (i.e., 1 μm or more).
As shown in FIG. 3, the electrolytic plating layer 15 is formed on the electroless plating layer 14, and then the electroless plating layer 14 is etched to provide a circuit pattern. More specifically, a dry film which has an opening for exposure of the circuit pattern region is layered on the insulating layer 12, and then the electrolytic plating layer 15 is formed in the opening. Subsequently, the region of the electroless plating layer 14 on which the electrolytic plating layer 15 is not formed is removed through flash etching, thus providing the circuit pattern.
However, since the circuit pattern which is prepared through the conventional semi-additive process protrudes from the insulating layer 12 in an embossed manner, the circuit pattern is apt to separate from the insulating layer 12. In particular, as the circuit pattern becomes fine, a contact area between the insulating layer 12 and the circuit pattern is reduced, with the result that an adhesive force at the contact area is diminished and thus the separation of the circuit pattern is intensified. In a multilayered printed circuit board, the separation of the circuit pattern formed on the outermost layer seriously decreases reliability of the printed circuit board.
Recently, new processes for overcoming the above problems are continuously being proposed. Among them, a LPP (Laser Patterning Process) is attracting attention, and is performed in such a manner that trenches are formed on an insulating layer and plating, polishing and etching processes are executed to form a circuit pattern.
FIGS. 3 to 7 are cross-sectional views sequentially showing a conventional LPP forming a circuit pattern. With reference to these drawings, the conventional LPP is to described below.
As shown in FIG. 4, pattern trenches 18a and a via trench 19a are formed using a laser in an insulating layer 17 including a metal layer 16 layered on one side thereof.
As shown in FIG. 5, an electroless plating layer 20 is deposited not only on the insulating layer 17 but also on inner surfaces of the trenches 18a and 19a. 
As shown in FIG. 6, an electrolytic plating layer 21 is deposited on the electroless plating layer 20.
Finally, as shown in FIG. 7, the portions of electroless plating layer 20 and the electrolytic plating layer 21 which are protruding from the insulating layer 17 are removed using an etching process or a grinding process, thus providing an embedded circuit pattern 18 including vias 19 therein.
Manufacturing a printed circuit board using LPP is advantageous because it is possible to prevent the separation of the circuit pattern 18 because the circuit pattern 18 is embedded in the printed circuit board. However, LPP requires an additional grinding process in order to reduce a difference in plating thicknesses between a region with the trenches 18a and 19a and a region without the trenches, and a process of forming the trenches 18a and 19a and a grinding process must be executed at every layer, thus causing extension of lead time. In addition, since process machinery which is used in the formation of the trenches 18a and 19a is expensive, manufacturing costs are correspondingly increased.
Furthermore, although it is also possible to form a fine circuit by forming trenches using an imprint process, the interlayer alignment significantly deteriorates, thus precluding application to a build-up board.